Professor

carl.sechen@utdallas.edu
Phone: 9728351611
Office: ECSN 4.902

Research Website

EDUCATION

Ph.D. in Electrical Engineering, University of California, Berkeley, 1987 M.S. in Electrical Engineering, Massachusetts Institute of Technology, 1977 B.E.E. in Electrical Engineering, University of Minnesota, 1975

OVERVIEW

Prof. Sechen was named an IEEE Fellow in 2002 for contributions to placement and routing of integrated circuits. Prof. Sechen received the Distinguished Teaching Award for the Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, 2014. His research interests center primarily on the design and computer-aided design of digital and analog integrated circuits.

RESEARCH INTEREST

My research interests center primarily on the design and computer-aided design of digital and analog integrated circuits. Ongoing projects include the design of secure ICs that cannot be re-verse engineered. We are continuing the development of the TRAP (TRAnsistor-level Program-mable) fabric that implements 10X more logic in the same area compared to lookup-table based FPGAs and eFPGAs, making it the first practical approach to secure hardware via IC redaction.

Honors and Awards

• Best Paper Award at the 2017 IEEE PhD Research in Microelectronics and Electronics Conference (PRIME), for the paper “Improved Lagrangian Relaxation-based Gate Size and VT Assignment for Very Large Circuits”, Bariloche, Argentina, February 2017.
• Nominated for a Best Paper Award for: “A Field Programmable Transistor Array Featuring Single-Cycle Partial/Full Dynamic Reconfiguration”, Proc. of Design Automation and Test in Europe (DATE) Conference, March 27-31, 2017, Lausanne, Switzerland.
• Nominated for UTD’s President’s Teaching Excellence Award for Graduate/Professional Instruction, 2020.
• Received the Graduate Teaching Excellence Award from the ECE Department at UT Dallas, May 2024.
• Received the Distinguished Teaching Award for the Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, 2014.
• Received the Distinguished Teacher of the Year Award, Dept. of Electrical Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, 2008.
• Elected IEEE Life Fellow in 2002
• Elected a Fellow of Asia-Pacific Artificial Intelligence Association (AAIA)
• Received the Outstanding Research Advisor Award, Department of Electrical Engineering, University of Washington, 2002.
• Received the Best Project Award, NSF Center for the Design of Digital and Analog ICs (CDADIC), July 2002.
• Received the Semiconductor Research Corporation’s 2001 SRC Inventor’s Recognition Award
• Received the Semiconductor Research Corporation’s 1994 SRC Technical Excellence Award
• Received the Semiconductor Research Corporation’s 1988 SRC Inventor’s Recognition Award

Publications

1. A. Fowler, S. Mohammed, M. Shihab, T. Broadfoot, P. Beerel, C. Sechen, and Y. Makris, “A TRAP for SAT: On the Imperviousness of a Transistor-Level Programmable Fabric to Satisfiability Attacks”, Transactions on Cryptographic Hardware and Embedded Systems 2025, Issue 2.
2. A. Jain, T. Broadfoot, Y. Makris and C. Sechen, “Modeling Bidirectional Switches for Enabling Logic Equivalence Checking in a Transistor-Level Programmable Fabric,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 2025, Vol. 44, No. 1, pp. 385-389.
3. Roshan, C. Sechen, et al., “A MEMS-Assisted Temperature Sensor with 20μK Resolution, Conversion Rate of 200S/s and FOM of 0.04pJK”, IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 185-197, January 2017.
4. A. Fowler, C. Sechen and Y. Makris, “An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists”, International Test Conference (ITC), Sept. 21-26, 2025, San Diego, CA.
5. A. Jain, T. Broadfoot, Y. Makris, and C. Sechen, “Testing a Transistor-Level Programmable Fabric: Challenges and Solutions”, Proc. IEEE VLSI Test Symposium (VTS), Tempe, AZ, April 22-24, 2024.
6. A. Jain, T. Broadfoot, Y. Makris, and C. Sechen, “Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric”, Proc. Design Automation and Test in Europe (DATE) Conference, Antwerp, Belgium, April 17-19, 2023.
7. V. Salimath and C. Sechen, “Essential Standard Cell Library Composition”, Proc. 15th IEEE Dallas Circuits and Systems Conference (DCAS 2022), June 17-19, 2022, Dallas, TX.
8. L. Nahar, J. Rajendran, Y. Makris and C. Sechen, “MTBoM: Metal Trace to Bill of Materials Generation for PCB Reverse Engineering”, Proc. 15th IEEE Dallas Circuits and Systems Conference (DCAS 2022), June 17-19, 2022, Dallas, TX.
9. Q. Huang, J. Tian, T. Broadfoot, X. Xu, B. Hu, M. Shihab, A. Jain, V. Salimath, Y. Makris and C. Sechen”, Proc. 15th IEEE Dallas Circuits and Systems Conference (DCAS 2022), June 17-19, 2022, Dallas, TX.
10. M. Shihab, J. Tian, G. Reddy, B. Hu, W. Swartz Jr., B. Schaefer, C. Sechen and Y. Makris, “CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric”, Proc. IEEE International Symposium on Circuits & Systems (ISCAS), May 17-20, 2020, Seville, Spain.
11. V. Salimath and C. Sechen, “Optimal Standard Cell Library Composition for 7nm”, Proc. IEEE International Symposium on Circuits & Systems (ISCAS), May 17-20, 2020, Seville, Spain.
12. M. Shihab, B. Ramanidharan, S. Tellakula, G. Reddy, J. Tian, C. Sechen, and Y. Makris, “ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric”, Proc. 8th IEEE VLSI Test Symposium (VTS’20), April 5-8, 2020, San Diego, CA.
13. B. Hu, M. Shihab, Y. Makris, B. Schaefer and C. Sechen, “An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs”, Proc. Design Automation in Europe Conference (DATE), March 9-13, 2020, Grenoble, France.
14. B. Hu, M. Shihab, Y. Makris, B. Schaefer and C. Sechen, “Extending the Lifetime of Coarse-grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage”, 2019 International Conference on Field-Programmable Technology (FPT’19), December 9-13, 2019 Tianjin, China.
15. B. Hu, J. Tian, M. Shihab, G. Reddy, W. Swartz, Y. Makris, B. Schaefer, and C. Sechen, “Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA”, Proc. Great Lakes Symposium on VLSI (GLSVLSI), Washington, D.C., USA, May 9-11, 2019.
16. M. Shihab, G. Reddy, J. Tian, B. Hu, W. Swartz, B. Carrion Schaefer, C. Sechen, Y. Makris, “Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming,” Proc. of Design Automation and Test in Europe (DATE) Conference, March 25-29, 2019, Florence, Italy.
17. A. Yella, S. Gunturi and C. Sechen, “Are Standalone Gate Size and VT Optimization Tools Useful?”, Proc. IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE), Devices, Circuits, and Systems Track, Windsor, ON, Canada, April 30 – May 3, 2017.
18. T. Broadfoot, C. Sechen and J. Rajendran, “On Designing Optimal Camouflaged Layouts”, Proc. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 1-4, 2017, McLean, VA.
19. A. Yella and C. Sechen, “Improved Lagrangian Relaxation-based Gate Size and VT Assign-ment for Very Large Circuits, Proc. IEEE PhD Research In Microelectronics and Electronics Conference Latin America (PRIME), Bariloche, Argentina, February 20-23, 2017. BEST PAPER AWARD
20. J. Tian, G. Reddy, J. Wang, W. Swartz, Y. Makris and C Sechen, “A Field Programmable Transistor Array Featuring Single-Cycle Partial/Full Dynamic Reconfiguration”, Proc. of Design Automation and Test in Europe (DATE) Conference, March 27-31, 2017, Lausanne, Switzerland. NOMINATED FOR BEST PAPER AWARD
21. M. Roshan, C. Sechen, et al., “Dual-MEMS Resonator Temperature-to-Digital Converter with 39µK Resolution and a FoM of 0.11pJK2”, Proc. Int. Solid-State Circuits Conf. (ISSCC), Feb. 2016, San Francisco, CA.